Exemplary embodiments relate generally to a semiconductor memory device and a method of operating the same and, more particularly, to a semiconductor memory device including nonvolatile memory cells and a method of operating the same.
In order to increase the data storage capacity, the multi-level cell technology, using multiple threshold voltage levels per cell to allow more bits to be stored, is being developed.
If n-bit data is stored in one memory cell, the threshold voltages of the memory cells are distributed in 2n levels. In addition, the data stored in the memory cells is deleted by an erase operation. The threshold voltages of the memory cells on which the erase operation has been performed are distributed at the lowest level, and they typically have a value lower than 0 V.
That is, the threshold voltages of the memory cells are lowered up to the lowest level through the erase operation. Since the threshold voltages distributed in different levels are lowered to a low level, the threshold voltages of the memory cells on which the erase operation has been performed have a wide distribution. If the threshold voltage distribution is wide in an erase state, the characteristic of a program operation may be degraded.
For example, if memory cells having the lowest threshold voltage in a threshold voltage distribution of an erase state are programmed up to the highest threshold voltage in a program state distribution, interference to surrounding memory cells may increase, and thus a shift in the threshold voltages of the surrounding memory cells may occur.